This project set out to evaluate different design and simulation tools in the context of digital logic, to find a tool that could help students pivot their skill from basic logic design into the more technical use of Hardware Definition Languages (HDLs). It found that most tools lack functionality to translate into a HDL and those that do are difficult to setup for a first time user. The consequence of this finding was to create a web app, developed as a series of iterative prototypes, with functionality to draw, simulate and convert logic diagrams into Verilog. User testing showed it successfully fulfilled the aims of a lightweight graphical app that could simulate logic and convert to a HDL. Subsequent interest in the artefact led to a revised set of aims and continued development with the intent for the artefact to be used as the digital logic learning tool in the University’s Computer Architecture module.
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